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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad5241/ad5242 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 functional block diagram rdac register 1 addr decode 8 pwr-on reset serial input register ad5241 shdn v dd v ss sda scl gnd a 1 w 1 b 1 o 1 o 2 register 2 ad0 ad1 rdac register 1 addr decode 8 pwr-on reset serial input register ad5242 shdn v dd v ss sda scl gnd a 1 w 1 b 1 a 2 w 2 b 2 rdac register 2 o 2 o 1 register 1 ad0 ad1 features 256 position 10 k , 100 k , 1 m low tempco 30 ppm/ c internal power on midscale preset single supply 2.7 v to 5.5 v or dual supply 2.7 v for ac or bipolar operation i 2 c-compatible interface with reaback capability extra programmable logic outputs applications multimedia, video and audio communications mechanical potentiometer replacement instrumentation: gain, offset adjustment programmable voltage-to-current conversion line impedance matching general description the ad5241/ad5242 provides a single-/dual-channel, 256- position digitally controlled variable resistor (vr) device. these devices perform the same electronic adjustment function as a potentiometer, trimmer or variable resistor. each vr offers a completely programmable value of resistance, between the a terminal and the wiper, or the b terminal and the wiper. for ad5242, the fixed a-to-b terminal resistance of 10 k ? , 100 k ? or 1 m ? has a 1% channel-to-channel matching tolerance. nominal temperature coefficient of both parts is 30 ppm/ c. wiper position programming defaults to midscale at system power on. once powered, the vr wiper position is programmed by an i 2 c-compatible 2-wire serial data interface. both parts have available two extra programmable logic outputs that enable users to drive digital loads, logic gates, led drivers, and analog switches in their system. the ad5241/ad5242 is available in surface-mount (so-14/-16) packa ges and, for ultracompact solutions, tssop-14/-16 pack- ages. all parts are guaranteed to operate over the extended industrial temperature range of ?0 c to +85 c. for 3-wire, spi-compatible interface applications, please refer to ad5200, ad5201, ad5203, ad5204, ad5206, ad5231 * , ad5232 * , ad5235 * , ad7376, ad8400, ad8402, and ad8403 products. i 2 c -compatible 256-position digital potentiometers * nonvolatile digital potentiometer. i 2 c is a registered trademark of philips corporation.
rev. a C2C ad5241/ad5242?pecifications 10 k , 100 k , 1 m version parameter symbol conditions min typ 1 max unit dc characteristics, rheostat mode (specifications apply to all vrs.) resistor differential nonlinearity 2 r-dnl r wb , v a = nc ? 0.4 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = nc ? 0.5 +2 lsb nominal resistor tolerance ? rt a = 25 c, rab = 10 k ? ?0 +30 % ? rt a = 25 c, rab = 100 k ? /1 m ? ?0 +50 % resistance temperature coefficient r ab / ? tv ab = v dd , wiper = no connect 30 ppm/ c wiper resistance r w i w = v dd /r, v dd = 3 v or 5 v 60 120 ? dc characteristics, potentiometer divider mode (specifications apply to all vrs.) resolution n 8 bits differential nonlinearity 3 dnl ? 0.4 +1 lsb integral nonlinearity 3 inl 2 0.5 +2 lsb voltage divider temperature coefficient ? v w / ? t code = 80 h 5 ppm/ c full-scale error v wfse code = ff h ? ?.5 0 lsb zero-scale error v wzse code = 00 h 0 0.5 1 lsb resistor terminals voltage range 4 v a, b, w v ss v dd v capacitance 5 a, b c a, b f = 1 mhz, measured to gnd, code = 80 h 45 pf capacitance 5 wc w f = 1 mhz, measured to gnd, code = 80 h 60 pf common-mode leakage i cm v a = v b = v w 1na digital inputs input logic high (sda and scl) v ih 0.7 v dd v dd + 0.5 v input logic low (sda and scl) v il ?.5 +0.3 v dd v input logic high (ad0 and ad1) v ih v dd = 5 v 2.4 v dd v input logic low (ad0 and ad1) v il v dd = 5 v 0 0.8 v input logic high v ih v dd = 3 v 2.1 v dd v input logic low v il v dd = 3 v 0 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 5 c il 3pf digital output v ol i ol = 3 ma 0.4 v output logic low (sda) v ol i ol = 6 ma 0.6 v output logic low (o 1 and o 2 )v ol i sink = 1.6 ma 0.4 v output logic high (o 1 and o 2 )v oh i source = 40 a4v three-state leakage current (sda) i oz v in = 0 v or 5 v 1 a output capacitance 5 c oz 38 pf power supplies power single-supply range v dd range v ss = 0 v 2.7 5.5 v power dual-supply range v dd/ss range 2.3 2.7 v positive supply current i dd v ih = 5 v or v il = 0 v 0.1 50 a negative supply current i ss v ss = ?.5 v, v dd = +2.5 v +0.1 ?0 a power dissipation 6 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 0.5 250 w power supply sensitivity pss ?.01 +0.002 +0.01 %/% dynamic characteristics 5, 7, 8 bandwidth ? db bw_10 k ? r ab = 10 k ? , code = 80 h 650 khz bw_100 k ? r ab = 100 k ? , code = 80 h 69 khz bw_1 m ? r ab = 1 m ? , code = 80 h 6 khz total harmonic distortion thd w v a = 1 v rms + 2 v dc, 0.005 % v b = 2 v dc, f = 1 khz v w settling time t s v a = v dd , v b = 0 v, 1 lsb error band, 2 s r ab = 10 k ? resistor noise voltage e n_wb r wb = 5 k ? , f = 1 khz 14 nv hz (v dd = 3 v 10% or 5 v 10%, v a = +v dd , v b = 0 v, ?0 c < t a < +85 c unless otherwise noted.)
rev. a C3C ad5241/ad5242 parameter symbol conditions min typ 1 max unit interface timing characteristics (applies to all parts. 5, 9 ) scl clock frequency f scl 0 400 khz t buf bus free time bet ween t 1 1.3 s stop and start t hd; sta hold time (repeated start) t 2 after this period the first clock 600 ns pulse is generated. t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 50 s t su; sta setup time for start condition t 5 600 ns t hd; dat data hold time t 6 900 ns t su; dat data setup time t 7 100 ns t r rise time of both t 8 300 ns sda and scl signals t f fall time of both sda and scl signals t 9 300 ns t su; sto setup time for stop condition t 10 notes 1 typicals represent average readings at 25 c, v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. see figure 10 test circuit. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. see figure 9 test circuit. 4 resistor terminals a, b, w have no limitations on polarity with respect to each other. 5 guaranteed by design and not subject to production test. 6 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 7 bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. the lowest r value results in the fa stest settling time and highest band- width. the highest r value results in the minimum overall power consumption. 8 all dynamic characteristics use v dd = 5 v. 9 see timing diagram for location of measured values. specifications subject to change without notice.
rev. a ad5241/ad5242 C4C absolute maximum ratings * (t a = 25 c, unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 , +7 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v , 7 v v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v a , v b , v w to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd a x ? x , a x ? x , b x ? x at 10 k ? in tssop-14 . . . 5.0 ma * a x ? x , a x ? x , b x ? x at 100 k ? in tssop-14 . . 1.5 ma * a x ? x , a x ? x , b x ? x at 1 m ? in tssop-14 . . . 0.5 ma * digital input voltage to gnd . . . . . . . . . . . . . . . . . . 0 v, 7 v operating temperature range . . . . . . . . . . . ?0 c to +85 c thermal resistance ja soic (so-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 c/w soic (so-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 c/w tssop-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 c/w tssop-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 c/w maximum junction temperature (t j max) . . . . . . . . . . 150 c package power dissipation p d = (t j max ?t a )/ ja storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c lead temperatures r-14, r-16, ru-14, ru-16 (vapor phase, 60 sec) . . 215 c r-14, r-16, ru-14, ru-16 (infrared, 15 sec) . . . . . . 220 c * max current increases at lower resistance and different packages. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5241/ad5242 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide number of end to end temperature package package #devices per model channels r ab ( ) range ( c) description option container ad5241br10 1 10 k ?0 to +85 so-14 r-14 56 ad5241br10-reel7 1 10 k ?0 to +85 so-14 r-14 1000 ad5241bru10-reel7 1 10 k ?0 to +85 tssop-14 ru-14 1000 ad5241br100 1 100 k ?0 to +85 so-14 r-14 56 ad5241br100-reel7 1 100 k ?0 to +85 so-14 r-14 1000 ad5241bru100-reel7 1 100 k ?0 to +85 tssop-14 ru-14 1000 ad5241br1m 1 1 m ?0 to +85 so-14 r-14 56 ad5241br1m-reel7 1 1 m ?0 to +85 so-14 r-14 1000 ad5241bru1m-reel7 1 1 m ?0 to +85 tssop-14 ru-14 1000 ad5242br10 2 10 k ?0 to +85 so-16 r-16a 48 ad5242br10-reel7 2 10 k ?0 to +85 so-16 r-16a 1000 ad5242bru10-reel7 2 10 k ?0 to +85 tssop-16 ru-16 1000 ad5242br100 2 100 k ?0 to +85 so-16 r-16a 48 ad5242br100-reel7 2 100 k ?0 to +85 so-16 r-16a 1000 ad5242bru100-reel7 2 100 k ?0 to +85 tssop-16 ru-16 1000 ad5242br1m 2 1 m ?0 to +85 so-16 r-16a 48 AD5242BR1M-REEL7 2 1 m ?0 to +85 so-16 r-16a 1000 ad5242bru1m-reel7 2 1 m ?0 to +85 tssop-16 ru-16 1000 notes 1. the ad5241/ad5242 die size is 69 mil 78 mil, 5,382 sq. mil. contains 386 transistors for each channel. patent number 5495245 applies. 2. tssop packaged units are only available in 1,000-piece quantity tape and reel.
rev. a C5C ad5241/ad5242 ad5242 pin function descriptions pin mnemonic description 1o 1 logic output terminal o 1 2a 1 resistor terminal a 1 3w 1 wiper terminal w 1 4b 1 resistor terminal b 1 5v dd positive power supply, specified for opera- tion from 2.2 v to 5.5 v. 6 shdn active low, asynchronous connection of the wiper w to terminal b, and open circuit of terminal a. rdac register contents unchanged. shdn should tie to v dd if not used. 7 scl serial clock input 8 sda serial data input/output 9 ad0 programmable address bit for multiple package decoding. bits ad0 and ad1 provide four possible addresses. 10 ad1 programmable address bit for multiple package decoding. bits ad0 and ad1 provide four possible addresses. 11 dgnd common ground 12 v ss negative power supply, specified for operation from 0 v to ?.7 v. 13 o 2 logic output terminal o 2 14 b 2 resistor terminal b 2 15 w 2 wiper terminal w 2 16 a 2 resistor terminal a 2 ad5241 pin configuration top view (not to scale) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 nc = no connect w 1 b 1 v dd shdn scl sda o 1 nc o 2 v ss dgnd ad1 ad0 a 1 ad5241 ad5242 pin configuration top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 o 1 a 1 w 1 b 1 v dd shdn scl sda a 2 w 2 b 2 o 2 v ss dgnd ad1 ad0 ad5242 ad5241 pin function descriptions pin mnemonic description 1a 1 resistor terminal a 1 2w 1 wiper terminal w 1 3b 1 resistor terminal b 1 4v dd positive power supply, specified for opera- tion from 2.2 v to 5.5 v. 5 shdn active low, asynchronous connection of the wiper w to terminal b, and open circuit of terminal a. rdac register contents unchanged. shdn should tie to v dd if not used. 6 scl serial clock input 7 sda serial data input/output 8 ad0 programmable address bit for multiple package decoding. bits ad0 and ad1 provide four possible addresses. 9 ad1 programmable address bit for multiple package decoding. bits ad0 and ad1 provide four possible addresses. 10 dgnd common ground 11 v ss negative power supply, specified for operation from 0 v to ?.7 v. 12 o 2 logic output terminal o 2 13 nc no connect 14 o 1 logic output terminal o 1
rev. a ad5241/ad5242 C6C t 8 t 1 t 8 t 3 t 2 t 2 t 9 t 5 t 10 s p t 7 t 4 s p sda scl t 6 figure 1. detail timing diagram data of ad5241/ad5242 is accepted from the i 2 c bus in the following serial format: s 0 1 0 1 1 ad1 ad0 r/ w a a /b rs sd o 1 o 2 x x x a d7d6d5d4d3d2d1d0 a p slave address byte instruction byte data byte where: s = start condition p = stop condition a = acknowledge x = don? care ad1, ad0 = package pin programmable address bits. must be matched with the logic states at pins ad1 and ad0. r/ w = read enable at high and output to sda. write enable at low. a /b = rdac sub address select. ??for rdac1 and ??for rdac2. rs = midscale reset, active high. sd = shutdown in active high. same as shdn except inverse logic. o 1 , o 2 = output logic pin latched values. d7, d6, d5, d4, d3, d2, d1, d0 = data bits. 1 91 1 99 0 1 0 1 1 ad1 ad0 r/ w a /b rssdo1o2 x x x d7d6d5d4d3d2 d1d0 ack by ad5241 ack by ad5241 ack by ad5241 stop by master start by master frame 1 slave address byte frame 2 instruction byte frame 3 data byte scl sda figure 2. writing to the rdac serial register 1 91 9 0 1 0 1 1 ad1 ad0 r/ w d7 d6 d5 d4 d3 d2 d1 d0 ack by ad5241 no ack by master stop by master start by master frame 1 slave address byte frame 2 data byte from previously selected rdac register in write mode scl sda figure 3. reading data from a previously selected rdac register in write mode
rev. a code ?decimal 1 0.5 0 ?.5 ? rheostat mode differential nonlinearity ?lsb 256 224 192 160 128 96 64 32 0 v dd /v ss = 2.7v/0v v dd = 2.7v v dd = 5.5v v dd = 2.7v v dd /v ss = 5.5v/0v, 2.7v tpc 1. rdnl vs. code code decimal 1 0.5 0 0.5 1 rheostat mode integral nonlinearity lsb 224 192 160 128 96 64 32 0 256 v dd /v ss = 5.5v/0v, 2.7v v dd = 2.7v v dd = 5.5v v dd = 2.7v v dd /v ss = 2.7v/0v tpc 2. rinl vs. code code decimal 0.25 0.13 0.00 0.13 0.25 potentiometer mode differential nonlinearity lsb 256 224 192 160 128 96 64 32 0 v dd /v ss = 2.7v/0v, 5.5v/0v, 2.7v v dd = 2.7v v dd = 5.5v v dd = 2.7v tpc 3. dnl vs. code C7C typical performance characteristics ad5241/ad5242 code decimal 0.50 0.25 0.00 0.25 0.50 potentiometer mode integral nonlinearity lsb 256 224 160 128 64 32 0 192 96 v dd = 2.7v v dd = 5.5v v dd = 2.7v v dd /v ss = 2.7v v dd /v ss = 2.7v/0v, 5.5v/0v tpc 4. inl vs. code 10000 100 1 nominal resistance k 80 60 40 20 0 20 40 temperature c v dd = 2.7v t a = 25 c 10 1000 10k 1m 100k tpc 5. nominal resistance vs. temperature 10000 1000 100 10 1 i d d - supply current a 5 4 3 2 1 0 input logic voltage v v dd = 2.5v v dd = 3v v dd = 5v *.,' -,
0
rev. a ad5241/ad5242 C8C 0.1 0.01 0.001 shutdow n current a 80 60 40 20 0 20 40 temperature c r ab = 10k v dd = 5.5v tpc 7. shutdown current vs. temperature v dd /v ss = 2.7v/0v t a = 25 c 100k version code decimal 128 112 96 80 64 48 32 16 0 70 60 20 0 30 potentiometer mode tempco pp m/ c 50 40 30 10 10 20 10k version 10m version tpc 8. v wb / t potentiometer mode tempco code decimal 120 100 20 20 80 rheostat mode tempco pp m/ c 128 112 96 80 64 48 32 16 0 80 60 40 0 40 60 v dd /v ss = 2.7v/0v t a = 25 c 10k version 10m version 100k version tpc 9. r wb / t rheostat mode tempco t a = 25 c common mode volts 100 90 50 30 w iper resistance 5 4 3 2 1 0 1 2 3 80 70 60 40 20 10 v dd /v ss = 2.7v/0v 6 v dd /v ss = 2.7v/0v v dd /v ss = 5.5v/0v tpc 10. incremental wiper contact vs. v dd /v ss frequency khz 300 100 50 0 i d d supply current a 1000 100 10 150 200 250 e b c a d f a v dd /v ss = 5.5v/0v code = ff b v dd /vss = 3.3v/0v code = ff c v dd /v ss = 2.5v/0v code = ff d v dd /v ss = 5.5v/0v code = 55 e v dd /v ss = 3.3v/0v code = 55 f v dd /v ss = 2.5v/0v code = 55 tpc 11. supply current vs. frequency frequency hz 6 36 42 48 54 gain db 1m 100k 10k 1k 100 30 24 18 12 6 0 ff h 80 h 40 h 20 h 10 h 08 h 04 h 02 h 01 h tpc 12. ad5242 10 k ? gain vs. frequency vs. code
rev. a C9C ad5241/ad5242 operation the ad5241/ad5242 provides a single-/dual-channel, 256- position digitally controlled variable resistor (vr) device. the terms vr, rdac, and programmable resistor are commonly used interchangeably to refer to digital potentiometer. to program the vr settings, refer to the digital interface sec- tion. both parts have an internal power on preset that places the wiper in midscale during power-on, which simplifies the fault condition recovery at power-up. in addition, the shutdown shdn pin of ad5241/ad5242 places the rdac in an almost zero power consumption state where terminal a is open cir- cuited and the wiper w is connected to terminal b, resulting in only leakage current being consumed in the vr structure. during shutdown, the vr latch contents are maintained when the rdac is inactive. when the part is returned from shut- down, the stored vr setting will be applied to the rdac. sw shdn sw n 2 1 r r sw n 2 2 rdac latch & decoder r r ab /2 n b w digital circuitry omitted for clarity a sw 1 sw 0 r r d7 d6 d5 d4 d3 d2 d1 d0 shdn figure 4. ad5241/ad5242 equivalent rdac circuit programming the variable resistor rheostat operation the nominal resistance of the rdac between terminals a and b are available in 10 k ? , 100 k ? , and 1 m ? . the final two or three digits of the part number determine the nominal resistance value, e.g. 10 k ? = 10; 100 k ? = 100; 1 m ? = 1 m. the nominal resistance (r ab ) of the vr has 256 contact points accessed by the wiper terminal, plus the b terminal contact. the 8-bit data in the rdac latch is decoded to select one of the 256 possible settings. assume a 10 k ? part is used; the wiper? first connection starts at the b terminal for data 00 h . since there is a 60 ? wiper contact resistance, such connection yields a minimum of 60 ? resistance between terminals w and b. the second connection is the first tap point corresponds to 99 ? (r wb = r ab /256 + r w = 39 + 60) for data 01 h . the third connection is the next tap point representing 138 ? (39 2 + 60) for data 02 h and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10021 ? [r ab ?1 lsb + r w ]. figure 4 shows a simplified dia- gram of the equivalent rdac circuit where the last resistor string will not be accessed; therefore, there is 1 lsb less of the nominal resistance at full scale in addition to the wiper resistance. the general equation determining the digitally programmed resistance between w and b is: rd d rr wb ab w () =+ 256 (1) where: d is the decimal equivalent of the binary code between 0 and 255 which is loaded in the 8-bit rdac register. r ab is the nominal end-to-end resistance. r w is the wiper resistance contributed by the on-resistance of the internal switch. again, if r ab = 10 k ? and a terminal can be either open circuit or tied to w, the following output resistance at r wb will be set for the following rdac latch codes. frequency hz 6 36 42 48 54 gain db 100k 10k 1k 100 30 24 18 12 6 0 ff h 80 h 40 h 20 h 10 h 08 h 04 h 02 h 01 h tpc 13. ad5242 100 k ? gain vs. frequency vs. code frequency hz 6 36 42 48 54 gain db 100k 10k 1k 100 30 24 18 12 6 0 ff h 80 h 40 h 20 h 10 h 08 h 04 h 02 h 01 h *.,)% &#%#)/ ? gain vs. frequency vs. code
rev. a ad5241/ad5242 C10C dr wb (dec) ( ) output state 255 10021 full-scale (r wb 1 lsb + r w ) 128 5060 midscale 199 1 lsb 0 60 zero-scale (wiper contact resistance) note that in the zero-scale condition a finite wiper resistance of 60 ? is present. care should be taken to limit the current flow between w and b in this state to a maximum current of no more than 20 ma. otherwise, degradation or possible destruction of the internal switch contact can occur. similar to the mechanical potentiometer, the resistance of the rdac between the wiper w and terminal a also produces a digitally controlled resistance r wa . when these terminals are used, the b terminal can be opened or tied to the wiper termi- nal. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is: rd d rr wa ab w () =+ 256 256 (2) for r ab = 10 k ? and b terminal can be either open circuit or tied to w. the following output resistance r wa will be set for the following rdac latch codes. dr wa (dec) ( ) output state 255 99 full-scale 128 5060 midscale 1 10021 1 lsb 0 10060 zero-scale the typical distribution of the nominal resistance r ab from channel-to-channel matches within 1% for ad5242. device- to-device matching is process lot dependent and it is possible to have 30% variation. since the resistance element is processed in thin film technology, the change in r ab with temperature has no more than 30 ppm/ c temperature coefficient. programming the potentiometer divider voltage output operation the digital potentiometer easily generates output voltages at wiper-to-b and wiper-to-a to be proportional to the input volt- age at a-to-b. unlike the polarity of v dd v ss , which must be positive, voltage across a b, w a, and w b can be at either polarity provided that v ss is powered by a negative supply. if ignoring the effect of the wiper resistance for approximation, connecting a terminal to 5 v and b terminal to ground pro- duces an output voltage at the wiper-to-b starting at zero volt up to 1 lsb less than 5 v. each lsb of voltage is equal to the voltage applied across terminal ab divided by the 256 position of the potentiometer divider. since ad5241/ad5242 can be supplied by dual supplies, the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminals a and b is: vd d v d v wa b () =+ ? 256 256 256 (3) which can be simplified to vd d vv wabb () =+ 256 (4) where d is decimal equivalent of the binary code between 0 to 255 which is loaded in the 8-bit rdac register. for more accurate calculation including the effects of wiper resistance, v w can be found as: vd rd r v rd r v w wb ab a wa ab b () = () + () (5) where r wb ( d ) and r wa ( d ) can be obtained from equations 1 and 2. operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. unlike the rheo- stat mode, the output voltage is dependent on the ratio of the internal resistors r wa , r wb , and not the absolute values; there- fore, the temperature drift reduces to 5 ppm/ c. digital interface 2-wire serial bus the ad5241/ad5242 are controlled via an i 2 c-compatible serial bus. the rdacs are connected to this bus as slave devices. referring to figures 2 and 3, the first byte of ad5241/ad5242 is a slave address byte. it has a 7-bit slave address and a r/ w bit. the 5 msbs are 01011 and the following two bits are deter- mined by the state of the ad0 and ad1 pins of the device. ad0 and ad1 allow users to use up to four of these devices on one bus. the 2-wire i 2 c serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high, figure 2. the following byte is the slave address byte, frame 1, which consists of the 7-bit slave address followed by an r/ w bit (this bit determines whether data will be read from or written to the slave device). the slave whose address corresponds to the transmitted address will respond by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master will read from the slave device. if the r/ w bit is low, the master will write to the slave device. 2. a write operation contains an extra instruction byte more than the read operation. such instruction byte, frame 2, in write mode follows the slave address byte. the msb of the instruction byte labeled a /b is the rdac subaddress select. a low selects rdac1 and a high selects rdac2 for the dual-channel ad5242. set a /b to low for ad5241. the second msb, rs, is the midscale reset. a logic high of this bit moves the wiper of a selected rdac to the center tap where r wa = r wb . the third msb, sd, is a shutdown bit. a logic high on sd causes the rdac open circuit at terminal a while shorting wiper to terminal b. this operation yields almost a 0 ? in rheostat mode or zero volt in potentiometer mode. this sd bit serves the same function as the shdn pin except shdn pin reacts to active low. the following two
rev. a C11C ad5241/ad5242 bits are o 2 and o 1 . they are extra programmable logic out- put that users can use to drive other digital loads, logic gates, led drivers, and analog switches, etc. the three lsbs are don t care. see figure 2. 3. after acknowledging the instruction byte, the last byte in write mode is the data byte, frame 3. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl, figure 2. 4. unlike the write mode, the data byte follows immediately after the acknowledgment of the slave address byte in the read mode, frame 2. data is transmitted over the serial bus in sequences of nine clock pulses (slight difference with the write mode, there are eight data bits followed by a no acknowledge bit). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl, figure 3. 5. when all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low-to-high transition on the sda line while scl is high. in write mode, the master will pull the sda line high during the tenth clock pulse to establish a stop condition (see figure 2). in read mode, the master will issue a no acknowl- edge for the ninth clock pulse (i.e., the sda line remains high). the master will then bring the sda line low before the tenth clock pulse which goes high to establish a stop condition (see figure 3). a repeated write function gives the user flexibility to update the rdac output a number of times after addressing and instruct- ing the part only once. during the write cycle, each data byte will update the rdac output. for example, after the rdac has acknowledged its slave address and instruction bytes, the rdac output will be updated. if another byte is written to the rdac while it is still addressed to a specific slave device with the same instruction, this byte will update the output of the selected slave device. if different instructions are needed, the write mode has to start a whole new sequence with a new slave address, instruction, and data bytes transferred again. simi- larly, a repeated read function of the rdac is also allowed. multiple devices on one bus figure 5 shows four ad5242 devices on the same serial bus. each has a different slave address since the state of their ad0 and ad1 pins are different. this allows each rdac within each device to be written to or read from independently. the master device output bus line drivers are open-drain pull-downs in a fully i 2 c-compatible interface. note, a device will be addressed properly only if the bit information of ad0 and ad1 in the slave address byte matches with the logic inputs at pins ad0 and ad1 of that particular device. sda scl ad5242 ad1 ad0 sda scl r p r p sda scl ad5242 v dd ad1 ad0 sda scl ad1 ad0 ad5242 v dd sda scl ad5242 v dd ad1 ad0 master 5v figure 5. multiple ad5242 devices on one bus level-shift for bidirectional interface while most old systems may be operated at one voltage, a new component may be optimized at another. when they operate the same signal at two different voltages, a proper method of le vel- shifting is needed. for instance, one can use a 3.3 v e 2 prom to interface with a 5 v digital potentiometer. a level-shift scheme is needed in order to enable a bidirectional comm uni- cation so that the setting of the digital potentiometer can be stored to and retrieved from the e 2 prom. figure 6 shows one of the techniques. m1 and m2 can be n-ch fets 2n7002 or low threshold fdv301n if v dd falls below 2.5 v. r p r p sd g m1 sd g m2 3.3v e 2 prom r p r p 5v ad5242 scl2 sda2 v dd2 = 5v scl1 sda1 v dd2 = 3.3v figure 6. level-shift for different voltage devices operation in 1 2 v dd o1 v ss m p m n o 1 data in frame 2 of write mode figure 7. output stage of logic output o 1 readback rdac value ad5241/ad5242 allows user to read back the rdac values in read mode. however, for ad5242 dual channel device, the channel of interest is the one that is previously selected in write mode. in the case that users need to read the rdac values of both channels in ad5242, they can program the first subaddress in the write mode and then change to the read mode to read the first channel value. after that, they can change back to the write mode with the second subaddress and finally read the second channel value in the read mode again. note that it is not necessary for users to issue the frame 3 data byte in the write mode for subsequent readback operation. users should refer to figures 2 and 3 for the programming format. additional programmable logic output ad5241/ad5242 features additional programmable logic outputs, o 1 and o 2 , which can be used to drive digital load, analog switches, and logic gates. the logic states of o 1 and o 2 can be programmed in frame 2 of the write mode (see figure 2). figure 7 shows the output stage o 1 where the logic levels are equal to the supply levels and the current driving capability reaches tenths of ma. all digital inputs are protected with a series input resistor and parallel zener esd structures shown in figure 8. this applies to digital input pins sda, scl, and shdn .
rev. a ad5241/ad5242 C12C 340 logic v ss figure 8. esd protection of digital pins test circuits test circuits 1 to 9 define the test conditions used in the product specification table. v ms a w b dut v v+ = v dd 1lsb = v+/2 n test circuit 1. potentiometer divider nonlinearity error (inl, dnl) no connect i w v ms a w b dut test circuit 2. resistor position nonlinearity error (rheo- stat operation; r-inl, r-dnl) v ms1 i w = v dd /r nominal v ms2 v w r w = [v ms1 v ms2 ]/i w a w b dut test circuit 3. wiper resistance v ms % v dd % pss (%/%) = v+ = v dd 10% psrr (db) = 20 log v ms v dd ( ) v dd v a v ms a w b v+ test circuit 4. power supply sensitivity (pss, psrr) op279 w 5v b v out offset gnd offset bias a dut test circuit 5. inverting gain a,b,w v ss figure 9. esd protection of resistor terminals b a v in op279 w 5v v out offset gnd offset bias dut test circuit 6. noninverting gain +15v 15v w a 2.5v b v out offset gnd dut op42 v in test circuit 7. gain vs. frequency w b v ss to v dd dut i sw code = h r sw = 0.1v i sw 0.1v * ,
2
: w b v cm i cm a nc gnd nc v ss v dd dut test circuit 9. common-mode leakage current
rev. a C13C ad5241/ad5242 digital potentiometer selection guide number resolution power of vrs terminal interface nominal (number supply part per voltage data resistance of wiper current number package 1 range control 2 (k ) positions) (i dd ) packages comments ad5201 1 3 v, +5.5 v 3-wire 10, 50 33 40 a soic-10 full ac specs, dual supply, pwr-on-reset, low cost ad5220 1 5.5 v up/down 10, 50, 100 128 40 a pdip, so-8, soic-8 no rollover, pwr-on-reset ad7376 1 15 v, +28 v 3-wire 10, 50, 100, 1000 128 100 a pdip-14, sol-16, single 28 v or dual 15 v tssop-14 supply operation ad5200 1 3 v, +5.5 v 3-wire 10, 50 256 40 a soic-10 full ac specs, dual supply, pwr-on-reset ad8400 1 5.5 v 3-wire 1, 10, 50, 100 256 5 a so-8 full ac specs ad5241 1 3 v, +5.5 v 2-wire 10, 100, 1000 256 50 a so-14, tssop-14 i 2 c-compatible, tc < 50 ppm/ c ad5231 * 1 2.75 v, +5.5 v 3-wire 10, 50, 100 1024 10 a tssop-16 nonvolatile memory, direct program, i/d, 6 db settability ad5222 2 3 v, +5.5 v up/down 10, 50, 100, 1000 128 80 a so-14, tssop-14 no rollover, stereo, pwr-on- reset, tc < 50 ppm/ c ad8402 2 5.5 v 3-wire 1, 10, 50, 100 256 5 a pdip, so-14, full ac specs, na tssop-14 shutdown current ad5232 2 2.75 v, +5.5 v 3-wire 10, 50, 100 256 10 a tssop-16 nonvolatile memory, direct program, i/d, 6 db settability ad5242 2 3 v, +5.5 v 2-wire 10, 100, 1000 256 50 a so-16, tssop-16 i 2 c-compatible, tc < 50 ppm/ c ad5262 * 2 5 v, +12 v 3-wire 20, 50, 200 256 60 a tssop-16 medium voltage operation, tc < 50 ppm/ c ad5203 4 5.5 v 3-wire 10, 100 64 5 a pdip, sol-24, full ac specs, na tssop-24 shutdown current ad5233 * 4 2.75 v, +5.5 v 3-wire 10, 50, 100 64 10 a tssop-16 nonvolatile memory, direct program, i/d, 6 db settability ad5204 4 3 v, +5.5 v 3-wire 10, 50, 100 256 60 a pdip, sol-24, full ac specs, dual supply, tssop-24 pwr-on-reset ad8403 4 5.5 v 3-wire 1, 10, 50, 100 256 5 a pdip, sol-24, full ac specs, na tssop-24 shutdown current ad5206 6 3 v, +5.5 v 3-wire 10, 50, 100 256 60 a pdip, sol-24, full ac specs, dual supply, tssop-24 pwr-on-reset ad5260 1 5 v, +15 v 3-wire 20, 50, 200 256 60 a tssop-14 tc < 50 ppm/ c ad5207 2 3 v, +5.5 v 3-wire 10, 50, 100 256 40 a tssop-14 full ac specs, svo ad5235 2 2.75 v, +5.5 v 3-wire 25, 250 1024 20 a tssop-16 nonvolatile memory, tc < 50 ppm/ c notes * future product, consult factory for latest status. 1 vr stands for variable resistor. this term is used interchangeably with rdac, programmable resistor, and digital potentiometer. 2 3-wire interface is spi- and microwire-compatible. 2-wire interface is i 2 c-compatible.
rev. a ad5241/ad5242 C14C outline dimensions dimensions shown in inches and (mm). 16-lead tssop (ru-16) 16 9 8 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 16-lead soic (r-16a) 16 9 8 1 0.1574 (4.00) 0.1497 (3.80) 0.3937 (10.00) 0.3859 (9.80) 0.050 (1.27) bsc pin 1 0.2440 (6.20) 0.2284 (5.80) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 0.0500 (1.27) 0.0160 (0.41) 0.0099 (0.25) 0.0075 (0.19) 14-lead tssop (ru-14) 14 8 7 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 14-lead soic (r-14) 14 8 7 1 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 0.3444 (8.75) 0.3367 (8.55) 0.050 (1.27) bsc seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 0.0500 (1.27) 0.0160 (0.41) 0.0099 (0.25) 0.0075 (0.19)
rev. a C15C ad5241/ad5242 revision history location page data sheet changed from rev. 0 to rev. a. edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to functional block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 additions to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to figures 1, 2, 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 addition of readback rdac value and additional programmable logic output sections, and addition of new figure 7 (which changed succeeding figure numbers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 additions/edits to digital potentiometer selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
C16C printed in u.s.a. c00926C0C2/02(a)

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